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LTC2420 20-Bit Power No Latency ADC in SO-8
TM
FEATURES
s s s s s s
DESCRIPTIO
s s
s s s
s s s
20-Bit ADC in SO-8 Package 8ppm INL, No Missing Codes at 20 Bits 4ppm Full-Scale Error 0.5ppm Offset 1.2ppm Noise Digital Filter Settles in a Single Cycle. Each Conversion Is Accurate, Even After an Input Step Fast Mode: 16-Bit Noise, 12 Bits TUE at 100sps Internal Oscillator--No External Components Required 110dB Min, 50Hz/60Hz Notch Filter Reference Input Voltage: 0.1V to VCC Live Zero--Extended Input Range Accommodates 12.5% Overrange and Underrange Single Supply 2.7V to 5.5V Operation Low Supply Current (200A) and Auto Shutdown Pin Compatible with 24-Bit LTC2400
The LTC(R)2420 is a micropower 20-bit A/D converter with an integrated oscillator, 8ppm INL and 1.2ppm RMS noise that operates from 2.7V to 5.5V. It uses delta-sigma technology and provides a digital filter that settles in a single cycle for multiplexed applications. Through a single pin, the LTC2420 can be configured for better than 110dB rejection at 50Hz or 60Hz 2%, or it can be driven by an external oscillator for a user-defined rejection frequency in the range 1Hz to 800Hz. The internal oscillator requires no external frequency setting components. The converter accepts any external reference voltage from 0.1V to VCC. With its extended input conversion range of -12.5% VREF to 112.5% VREF, the LTC2420 smoothly resolves the offset and overrange problems of preceding sensors or signal conditioning circuits. The LTC2420 communicates through a flexible 3-wire digital interface which is compatible with SPI and MICROWIRETM protocols.
, LTC and LT are registered trademarks of Linear Technology Corporation. No Latency is a trademark of Linear Technology Corporation. MICROWIRE is a trademark of National Semiconductor Corporation.
APPLICATIO S
s s s s s s s s
Weight Scales Direct Temperature Measurement Gas Analyzers Strain Gauge Transducers Instrumentation Data Acquisition Industrial Process Control 4-Digit DVMs
TYPICAL APPLICATIO
2.7V TO 5.5V 1F 1 VCC LTC2420 REFERENCE VOLTAGE 0.1V TO VCC ANALOG INPUT RANGE -0.12VREF TO 1.12VREF 2 VREF SCK 7 FO 8
Total Unadjusted Error (3V Supply)
10 8
VCC
6 4 ERROR (ppm) 2 0 -2 -4 TA = -55C, -45C, 25C, 90C
= INTERNAL OSC/50Hz REJECTION = EXTERNAL CLOCK SOURCE = INTERNAL OSC/60Hz REJECTION
3 4
VIN GND
SDO CS
6 5
3-WIRE SPI INTERFACE
-6 -8 -10
2420 TA01
0
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VCC = 3V VREF = 2.5V 0.5 1.5 2.0 1.0 INPUT VOLTAGE (V) 2.5
2420 G01
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1
LTC2420
ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
PACKAGE/ORDER INFORMATION
TOP VIEW VCC 1 VREF 2 VIN 3 GND 4 8 7 6 5 FO SCK SDO CS
Supply Voltage (VCC) to GND .......................- 0.3V to 7V Analog Input Voltage to GND ....... - 0.3V to (VCC + 0.3V) Reference Input Voltage to GND .. - 0.3V to (VCC + 0.3V) Digital Input Voltage to GND ........ - 0.3V to (VCC + 0.3V) Digital Output Voltage to GND ..... - 0.3V to (VCC + 0.3V) Operating Temperature Range LTC2420C ............................................... 0C to 70C LTC2420I ............................................ - 40C to 85C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C
ORDER PART NUMBER LTC2420CS8 LTC2420IS8 S8 PART MARKING 2420 2420I
S8 PACKAGE 8-LEAD PLASTIC SO
TJMAX = 125C, JA = 130C/W
Consult factory for Military grade parts.
CONVERTER CHARACTERISTICS The q denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25C. (Notes 3, 4)
PARAMETER Resolution (No Missing Codes) Integral Nonlinearity Integral Nonlinearity (Fast Mode) Offset Error Offset Error (Fast Mode) Offset Error Drift Full-Scale Error Full-Scale Error (Fast Mode) Full-Scale Error Drift Total Unadjusted Error Output Noise Output Noise (Fast Mode) Normal Mode Rejection 60Hz 2% Normal Mode Rejection 50Hz 2% Power Supply Rejection, DC Power Supply Rejection, 60Hz 2% Power Supply Rejection, 50Hz 2% CONDITIONS 0.1V VREF VCC, (Note 5) VREF = 2.5V (Note 6) VREF = 5V (Note 6) VREF = 5V, VREF = 2.5V, 100 Samples/Second, fO = 2.048MHz 2.5V VREF VCC 2.5V < VREF < 5V, 100 Samples/Second, fO = 2.048MHz 2.5V VREF VCC 2.5V VREF VCC 2.5V < VREF < 5V, 100 Samples/Second, fO = 2.048MHz 2.5V VREF VCC VREF = 2.5V VREF = 5V VIN = 0V (Note 13) VREF = 5V, 100 Samples/Second, fO = 2.048MHz (Note 7) (Note 8) VREF = 2.5V, VIN = 0V VREF = 2.5V, VIN = 0V, (Notes 7, 15) VREF = 2.5V, VIN = 0V, (Notes 8, 15)
q q q q q q q q
MIN 20
TYP 4 8 40 0.5 3 0.04 4 10 0.04 8 16 6 20
MAX 10 20 250 10
UNITS Bits ppm of VREF ppm of VREF ppm of VREF ppm of VREF ppm of VREF ppm of VREF/C
10
ppm of VREF ppm of VREF ppm of VREF/C ppm of VREF ppm of VREF VRMS VRMS dB dB dB dB dB
110 110
130 130 100 110 110
2
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W
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LTC2420
A ALOG I PUT A D REFERE CE
SYMBOL VIN VREF CS(IN) CS(REF) IIN(LEAK) IREF(LEAK) PARAMETER Input Voltage Range Reference Voltage Range Input Sampling Capacitance Reference Sampling Capacitance Input Leakage Current Reference Leakage Current CS = VCC
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 3)
CONDITIONS (Note 14)
q q
VREF = 2.5V, CS = VCC
DIGITAL I PUTS A D DIGITAL OUTPUTS
SYMBOL VIH VIL VIH VIL IIN IIN CIN CIN VOH VOL VOH VOL IOZ PARAMETER High Level Input Voltage CS, FO Low Level Input Voltage CS, FO High Level Input Voltage SCK Low Level Input Voltage SCK Digital Input Current CS, FO Digital Input Current SCK Digital Input Capacitance CS, FO Digital Input Capacitance SCK High Level Output Voltage SDO Low Level Output Voltage SDO High Level Output Voltage SCK Low Level Output Voltage SCK High-Z Output Leakage SDO (Note 9) IO = - 800A IO = 1.6mA IO = - 800A (Note 10) IO = 1.6mA (Note 10) CONDITIONS 2.7V VCC 5.5V 2.7V VCC 3.3V 4.5V VCC 5.5V 2.7V VCC 5.5V
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 3)
MIN
q q q q q q
2.7V VCC 5.5V (Note 9) 2.7V VCC 3.3V (Note 9) 4.5V VCC 5.5V (Note 9) 2.7V VCC 5.5V (Note 9) 0V VIN VCC 0V VIN VCC (Note 9)
POWER REQUIRE E TS
SYMBOL VCC ICC PARAMETER Supply Voltage Supply Current Conversion Mode Sleep Mode
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 3)
CONDITIONS
q
CS = 0V (Note 12) CS = VCC (Note 12)
U
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MIN - 0.125 * VREF 0.1
TYP
MAX 1.125 * VREF VCC
UNITS V V pF pF
1 1.5
q q
- 100 - 100
1 1
100 100
nA nA
TYP
MAX
UNITS V V
2.5 2.0 0.8 0.6 2.5 2.0 0.8 0.6 -10 -10 10 10 10 10
V V V V V V A A pF pF V
q q q q q
VCC - 0.5 0.4 VCC - 0.5 0.4 -10 10
V V V A
MIN 2.7
TYP
MAX 5.5
UNITS V A A
q q
200 20
300 30
3
LTC2420 TI I G CHARACTERISTICS
SYMBOL fEOSC tHEO tLEO tCONV PARAMETER External Oscillator Frequency Range External Oscillator High Period External Oscillator Low Period Conversion Time FO = 0V FO = VCC External Oscillator (Note 11) Internal Oscillator (Note 10) External Oscillator (Notes 10, 11) (Note 10) (Note 9) (Note 9) (Note 9) Internal Oscillator (Notes 10, 12) External Oscillator (Notes 10, 11) (Note 9)
q q q q q q q q
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 3)
CONDITIONS 20-Bit Effective Resolution 12-Bit Effective Resolution
q q q q q q q
fISCK DISCK fESCK tLESCK tHESCK tDOUT_ISCK tDOUT_ESCK t1 t2 t3 t4 tKQMAX tKQMIN t5 t6
Note 1: Absolute Maximum Ratings are those values beyond which the life of the device may be impaired. Note 2: All voltage values are with respect to GND. Note 3: All voltages are with respect to GND. VCC = 2.7 to 5.5V unless otherwise specified. RSOURCE = 0. Note 4: Internal Conversion Clock source with the FO pin tied to GND or to VCC or to external conversion clock source with fEOSC = 153600Hz unless otherwise specified. Note 5: Guaranteed by design, not subject to test. Note 6: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 7: FO = 0V (internal oscillator) or fEOSC = 153600Hz 2% (external oscillator). Note 8: FO = VCC (internal oscillator) or fEOSC = 128000Hz 2% (external oscillator).
4
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MIN 2.56 2.56 0.2 0.2
TYP
MAX 307.2 2.048 390 390
UNITS kHz MHz s s ms ms ms kHz kHz
130.86 133.53 136.20 157.03 160.23 163.44 20510/fEOSC (in kHz) 19.2 fEOSC/8 45 250 250 1.23 1.25 1.28 192/fEOSC (in kHz) 24/fESCK (in kHz) 0 0 0 50 200 15 50 50 150 150 150 55 2000
Internal SCK Frequency Internal SCK Duty Cycle External SCK Frequency Range External SCK Low Period External SCK High Period Internal SCK 24-Bit Data Output Time External SCK 24-Bit Data Output Time CS to SDO Low Z CS to SDO High Z CS to SCK CS to SCK SCK to SDO Valid SDO Hold After SCK SCK Set-Up Before CS SCK Hold After CS
% kHz ns ns ms ms ms ns ns ns ns ns ns ns ns
(Note 10) (Note 9) (Note 5)
q q q q q q
Note 9: The converter is in external SCK mode of operation such that the SCK pin is used as digital input. The frequency of the clock signal driving SCK during the data output is fESCK and is expressed in kHz. Note 10: The converter is in internal SCK mode of operation such that the SCK pin is used as digital output. In this mode of operation the SCK pin has a total equivalent load capacitance CLOAD = 20pF. Note 11: The external oscillator is connected to the FO pin. The external oscillator frequency, fEOSC, is expressed in kHz. Note 12: The converter uses the internal oscillator. FO = 0V or FO = VCC. Note 13: The output noise includes the contribution of the internal calibration operations. Note 14: For reference voltage values VREF > 2.5V the extended input of - 0.125 * VREF to 1.125 * VREF is limited by the absolute maximum rating of the Analog Input Voltage pin (Pin 3). For 2.5V < VREF 0.267V + 0.89 * VCC the input voltage range is - 0.3V to 1.125 * VREF. For 0.267V + 0.89 * VCC < VREF VCC the input voltage range is - 0.3V to VCC + 0.3V. Note 15: VCC (DC) = 4.1V, VCC (AC) = 2.8VP-P.
LTC2420 TYPICAL PERFOR A CE CHARACTERISTICS
Total Unadjusted Error (3V Supply)
10 8 6 4 VCC = 3V VREF = 2.5V 10 8 6 4
ERROR (ppm)
ERROR (ppm)
ERROR (ppm)
2 0 -2 -4 -6 -8 -10 0 0.5 1.5 2.0 1.0 INPUT VOLTAGE (V) 2.5
2420 G01
TA = -55C, -45C, 25C, 90C
Positive Input Extended Total Unadjusted Error (3V Supply)
10 8 6 4
ERROR (ppm)
VCC = 3V VREF = 2.5V
ERROR (ppm)
2 0 -2 -4 -6 -8 -10 2.50 2.55 2.60 2.65 2.70 INPUT VOLTAGE (V) 2.75 2.80 TA = -55C, -45C, 25C, 90C
2 0 -2 -4 -6 -8 -10 0 1 3 2 INPUT VOLTAGE (V) 4 5
2420 G05
ERROR (ppm)
Negative Input Extended Total Unadjusted Error (5V Supply)
10 8 6 4 ERROR (ppm) 2 0 -2 -4 -6 -8 -10 0 -0.05 -0.10 -0.15 -0.20 -0.25 -0.30 INPUT VOLTAGE (V)
2420 G07
VCC = 5V VREF = 5V
TA = 25C TA = 90C TA = -45C TA = -55C ERROR (ppm)
4 2 0 -2 -4 -6 -8 -10 5.00 TA = 90C 5.05 TA = 25C TA = -55C TA = -45C
OFFSET ERROR (ppm)
UW
2420 G04
INL (3V Supply)
VCC = 3V VREF = 2.5V
Negative Input Extended Total Unadjusted Error (3V Supply)
10 8 6 4 2 0 -2 -4 TA = -55C VCC = 3V VREF = 2.5V TA = 90C TA = 25C TA = -45C
2 0 -2 -4 -6 -8 -10 0 0.5 1.5 2.0 1.0 INPUT VOLTAGE (V) 2.5
2420 G02
TA = -55C, -45C, 25C, 90C
-6 -8 -10 0 -0.05 -0.10 -0.15 -0.20 -0.25 -0.30 INPUT VOLTAGE (V)
2420 G03
Total Unadjusted Error (5V Supply)
10 8 6 4 VCC = 5V VREF = 5V
INL (5V Supply)
10 8 6 4 2 0 -2 -4 -6 -8 -10 0 1 3 2 INPUT VOLTAGE (V) 4 5
2420 G06
VCC = 5V VREF = 5V
TA = -55C, -45C, 25C, 90C
TA = -55C, -45C, 25C, 90C
Positive Input Extended Total Unadjusted Error (5V Supply)
10 8 6 VCC = 5V VREF = 5V
150
Offset Error vs Reference Voltage
VCC = 5V TA = 25C
120
90
60
30
0
5.10 5.15 5.20 INPUT VOLTAGE (V)
5.25
5.30
0
1
3 4 2 REFERENCE VOLTAGE (V)
5
2420 G09
2420 G08
5
LTC2420 TYPICAL PERFOR A CE CHARACTERISTICS
RMS Noise vs Reference Voltage
60 50
RMS NOISE (ppm OF VREF)
OFFSET ERROR (ppm)
40 30 20 10 0 0 1 2 3 4 REFERENCE VOLTAGE (V) 5
2420 G10
RMS NOISE (ppm)
Noise Histogram
350 VCC = 5 =5 V 300 VREF 0 IN =
NUMBER OF READINGS RMS NOISE (ppm)
250 200 150 100 50 0 -2
2.50
OFFSET ERROR (ppm)
4 2 0 OUTPUT CODE (ppm)
Full-Scale Error vs Temperature
10 VCC = 5V VREF = 5V VIN = 5V 0 -25
FULL-SCALE ERROR (ppm)
FULL-SCALE ERROR (ppm)
5
FULL-SCALE ERROR (ppm)
0
-5
-10 -55 -30
70 -5 20 45 TEMPERATURE (C)
6
UW
VCC = 5V TA = 25C
6
2420G13
Offset Error vs VCC
10 VREF = 2.5V TA = 25C 10.0
RMS Noise vs VCC
VREF = 2.5V TA = 25C
5
7.5
0
5.0
-5
2.5
-10 2.7 3.2 3.7 4.2 VCC (V) 4.7 5.2 5.5
2420 G11
0 2.7 3.2 3.7 4.2 VCC (V) 4.7 5.2 5.5
2420 G12
RMS Noise vs Code Out
5.00 VCC = 5V VREF = 5V VIN = 0.3V TO 5.3V TA = 25C
10
Offset Error vs Temperature
VCC = 5V VREF = 5V VIN = 0V
3.75
5
0
1.25
-5
0 0 7FFFFF CODE OUT (HEX) FFFFFF
2420 G14
-10 -55 -30
70 -5 20 45 TEMPERATURE (C)
95
120
2420 G15
Full-Scale Error vs Reference Voltage
10
Full-Scale Error vs VCC
VREF = 2.5V VIN = 2.5V TA = 25C
5
-50 -75 -100 -125 -150 VCC = 5V VIN = VREF 0 1 2 3 4 REFERENCE VOLTAGE (V) 5
2420 G17
0
-5
-10 2.7 3.2 3.7 4.2 VCC (V) 4.7 5.2 5.5
2420 G18
95
120
2420 G16
LTC2420 TYPICAL PERFOR A CE CHARACTERISTICS
Conversion Current vs Temperature
230 220 VCC = 5.5V
SUPPLY CURRENT (A)
SUPPLY CURRENT (A)
210 200 VCC = 4.1V 190 180 170 160 150 - 55 -30 -5 70 45 20 TEMPERATURE (C) 95 120
2420 G19
REJECTION (dB)
VCC = 2.7V
Rejection vs Frequency at VCC
VCC = 4.1V VIN = 0V -20 TA = 25C FO = 0 REJECTION (dB) 0 0
REJECTION (dB)
REJECTION (dB)
-40 -60 -80
-100 -120 15200 15250 15300 15350 15400 15450 15500 FREQUENCY AT VCC (Hz)
2420 G22
Rejection vs Frequency at VIN
-60 -70 -80 REJECTION (dB) 0 -20
REJECTION (dB)
-90 -100 -110 -120 -130
REJECTION (dB)
-140 -120 15100 -12 -8 -4 0 4 8 12 INPUT FREQUENCY DEVIATION FROM NOTCH FREQUENCY (%)
2420 G25
UW
Sleep Current vs Temperature
30 -20
Rejection vs Frequency at VCC
VCC = 4.1V VIN = 0V T = 25C -40 F A = 0 O -60
20
VCC = 2.7V VCC = 5V
-80
10
-100
0 -55 -30
-5 20 45 70 TEMPERATURE (C)
95
120
-120
1
50
150 200 100 FREQUENCY AT VCC (Hz)
250
2420 G21
2420 G20
Rejection vs Frequency at VCC
VCC = 4.1V VIN = 0V -20 TA = 25C FO = 0 -40 -60 -80 0 -20 -40 -60 -80
Rejection vs Frequency at VIN
VCC = 5V VREF = 5V VIN = 2.5V FO = 0
-100 -120 1 100 10k FREQUENCY AT VCC (Hz) 1M
2420 G23
-100 -120 1 50 100 150 200 FREQUENCY AT VIN (Hz) 250
2420 G24
Rejection vs Frequency at VIN
VCC = 5V VREF = 5V VIN = 2.5V FO = 0
Rejection vs Frequency at VIN
0 -20 -40 -60 -80 -100
-40 -60 -80
-100 SAMPLE RATE = 15.36kHz 2% 15200 15300 15400 FREQUENCY AT VIN (Hz) 15500
2420 G26
-120 -140 0 fS/2 INPUT FREQUENCY
2420 F27
fS
7
LTC2420 TYPICAL PERFOR A CE CHARACTERISTICS
INL vs Output Rate
20 VCC = 5V VREF = 5V FO = EXTERNAL TUE RESOLUTION (BITS) 20
18 TUE RESOLUTION (BITS)
16
TA = -45C TA = 25C
16 TA = -45C 14 TA = 25C 12 TA = 90C
RESOLUTION (BITS)
14 TA = 90C 12
10
0
10 20 30 40 50 60 70 80 90 100 OUTPUT RATE (Hz)
2420 G28
PIN FUNCTIONS
VCC (Pin 1): Positive Supply Voltage. Bypass to GND (Pin 4) with a 10F tantalum capacitor in parallel with 0.1F ceramic capacitor as close to the part as possible. VREF (Pin 2): Reference Input. The reference voltage range is 0.1V to VCC. VIN (Pin 3): Analog Input. The input voltage range is - 0.125 * VREF to 1.125 * VREF. For VREF > 2.5V the input voltage range may be limited by the pin absolute maximum rating of - 0.3V to VCC + 0.3V. GND (Pin 4): Ground. Shared pin for analog ground, digital ground, reference ground and signal ground. Should be connected directly to a ground plane through a minimum length trace or it should be the single-point-ground in a single point grounding system. CS (Pin 5): Active LOW Digital Input. A LOW on this pin enables the SDO digital output and wakes up the ADC. Following each conversion, the ADC automatically enters the Sleep mode and remains in this low power state as long as CS is HIGH. A LOW on CS wakes up the ADC. A LOW-to-HIGH transition on this pin disables the SDO digital output. A LOW-to-HIGH transition on CS during the Data Output transfer aborts the data transfer and starts a new conversion. SDO (Pin 6): Three-State Digital Output. During the data output period this pin is used for serial data output. When the chip select CS is HIGH (CS = VCC), the SDO pin is in a high impedance state. During the Conversion and Sleep periods, this pin can be used as a conversion status output. The conversion status can be observed by pulling CS LOW. SCK (Pin 7): Bidirectional Digital Clock Pin. In Internal Serial Clock Operation mode, SCK is used as digital output for the internal serial interface clock during the data output period. In External Serial Clock Operation mode, SCK is used as digital input for the external serial interface. A weak internal pull-up is automatically activated in Internal Serial Clock Operation mode. The Serial Clock mode is determined by the level applied to SCK at power up and the falling edge of CS. FO (Pin 8): Frequency Control Pin. Digital input that controls the ADC's notch frequencies and conversion time. When the FO pin is connected to VCC (FO = VCC), the converter uses its internal oscillator and the digital filter's first null is located at 50Hz. When the FO pin is connected to GND (FO = OV), the converter uses its internal oscillator and the digital filter first null is located at 60Hz. When FO is driven by an external clock signal with a frequency fEOSC, the converter uses this signal as its clock and the digital filter first null is located at a frequency fEOSC/2560.
8
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INL vs Output Rate
VCC = 3V VREF = 2.5V FO = EXTERNAL
24
Resolution vs Output Rate
VCC = 5V VREF = 5V fO = EXTERNAL TA = 25C TA = 90C TA = -45C
18
22
20
18
10
16
0
10 20 30 40 50 60 70 80 90 100 OUTPUT RATE (Hz)
2420 G29
0 7.5
25
75 50 OUTPUT RATE (Hz)
100
2420 G30
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LTC2420
FU CTIO AL BLOCK DIAGRA W
INTERNAL OSCILLATOR AUTOCALIBRATION AND CONTROL FO (INT/EXT) SDO ADC SERIAL INTERFACE DECIMATING FIR SCK CS VREF
2420 FD
VCC GND
VIN
TEST CIRCUITS
VCC 3.4k
SDO 3.4k CLOAD = 20pF
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DAC
SDO CLOAD = 20pF
Hi-Z TO VOH VOL TO VOH VOH TO Hi-Z
2420 TC01
Hi-Z TO VOL VOH TO VOL VOL TO Hi-Z
2420 TC02
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LTC2420
APPLICATIO S I FOR ATIO
The LTC2420 is pin compatible with the LTC2400. The two devices are designed to allow the user to incorporate either device in the same design with no modifications. While the LTC2420 output word length is 24 bits (as opposed to the 32-bit output of the LTC2400), its output clock timing can be identical to the LTC2400. As shown in Figure 1, the LTC2420 data output is concluded on the falling edge of the 24th serial clock (SCK). In order to maintain drop-in compatibility with the LTC2400, it is possible to clock the LTC2420 with an additional 8 serial clock pulses. This results in 8 additional output bits which are always logic HIGH. Converter Operation Cycle The LTC2420 is a low power, delta-sigma analog-todigital converter with an easy to use 3-wire serial interface. Its operation is simple and made up of three states. The converter operating cycle begins with the conversion, followed by a low power sleep state and concluded with the data output (see Figure 2). The 3-wire interface consists of serial data output (SDO), a serial clock (SCK) and a chip select (CS). Initially, the LTC2420 performs a conversion. Once the conversion is complete, the device enters the sleep state. While in this sleep state, power consumption is reduced by an order of magnitude. The part remains in the sleep state as long as CS is logic HIGH. The conversion result is held indefinitely in a static shift register while the converter is in the sleep state.
CS 8 SCK 8 8 8 (OPTIONAL)
SDO
EOC = 1
EOC = 0
CONVERSION
SLEEP
Figure 1. LTC2420 Compatible Timing with the LTC2400
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Once CS is pulled LOW, the device begins outputting the conversion result. There is no latency in the conversion result. The data output corresponds to the conversion just performed. This result is shifted out on the serial data out pin (SDO) under the control of the serial clock (SCK). Data is updated on the falling edge of SCK allowing the user to reliably latch data on the rising edge of SCK, see Figure 4. The data output state is concluded once 24 bits are read out of the ADC or when CS is brought HIGH. The device automatically initiates a new conversion cycle and the cycle repeats. Through timing control of the CS and SCK pins, the LTC2420 offers several flexible modes of operation (internal or external SCK and free-running conversion modes). These various modes do not require programming configuration registers; moreover, they do
CONVERT SLEEP 1 CS AND SCK 0 DATA OUTPUT
2420 F02
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Figure 2. LTC2420 State Transition Diagram
DATA OUT 4 STATUS BITS 20 DATA BITS DATA OUTPUT
EOC = 1 LAST 8 BITS ALWAYS 1 CONVERSION
2420 F01
LTC2420
APPLICATIO S I FOR ATIO
not disturb the cyclic operation described above. These modes of operation are described in detail in the Serial Interface Timing Modes section. Conversion Clock A major advantage delta-sigma converters offer over conventional type converters is an on-chip digital filter (commonly known as Sinc or Comb filter). For high resolution, low frequency applications, this filter is typically designed to reject line frequencies of 50Hz or 60Hz plus their harmonics. In order to reject these frequencies in excess of 110dB, a highly accurate conversion clock is required. The LTC2420 incorporates an on-chip highly accurate oscillator. This eliminates the need for external frequency setting components such as crystals or oscillators. Clocked by the on-chip oscillator, the LTC2420 rejects line frequencies (50Hz or 60Hz 2%) a minimum of 110dB. Ease of Use The LTC2420 data output has no latency, filter settling or redundant data associated with the conversion cycle. There is a one-to-one correspondence between the conversion and the output data. Therefore, multiplexing an analog input voltage is easy. The LTC2420 performs offset and full-scale calibrations every conversion cycle. This calibration is transparent to the user and has no effect on the cyclic operation described above. The advantage of continuous calibration is extreme stability of offset and full-scale readings with respect to time, supply voltage change and temperature drift. Power-Up Sequence The LTC2420 automatically enters an internal reset state when the power supply voltage VCC drops below approximately 2.2V. This feature guarantees the integrity of the conversion result and of the serial interface mode selection which is performed at the initial power-up. (See the 2-wire I/O sections in the Serial Interface Timing Modes section.) When the VCC voltage rises above this critical threshold, the converter creates an internal power-on-reset (POR) signal with duration of approximately 0.5ms. The POR
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signal clears all internal registers. Following the POR signal, the LTC2420 starts a normal conversion cycle and follows the normal succession of states described above. The first conversion result following POR is accurate within the specifications of the device. Reference Voltage Range The LTC2420 can accept a reference voltage from 0V to VCC. The converter output noise is determined by the thermal noise of the front-end circuits, and as such, its value in microvolts is nearly constant with reference voltage. A decrease in reference voltage will not significantly improve the converter's effective resolution. On the other hand, a reduced reference voltage will improve the overall converter INL performance. The recommended range for the LTC2420 voltage reference is 100mV to VCC. Input Voltage Range The converter is able to accommodate system level offset and gain errors as well as system level overrange situations due to its extended input range, see Figure 3. The LTC2420 converts input signals within the extended input range of - 0.125 * VREF to 1.125 * VREF. For large values of VREF, this range is limited by the absolute maximum voltage range of - 0.3V to (VCC + 0.3V). Beyond this range, the input ESD protection devices begin to turn on and the errors due to the input leakage current increase rapidly. Input signals applied to VIN may extend below ground by - 300mV and above VCC by 300mV. In order to limit any
VCC + 0.3V 9/8VREF VREF ABSOLUTE MAXIMUM INPUT RANGE 1/2VREF NORMAL INPUT RANGE EXTENDED INPUT RANGE 0 -1/8VREF -0.3V
2420 F03
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Figure 3. LTC2420 Input Range
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LTC2420
APPLICATIO S I FOR ATIO
fault current, a resistor of up to 25k may be added in series with the VIN pin without affecting the performance of the device. In the physical layout, it is important to maintain the parasitic capacitance of the connection between this series resistance and the VIN pin as low as possible; therefore, the resistor should be located as close as practical to the VIN pin. The effect of the series resistance on the converter accuracy can be evaluated from the curves presented in the Analog Input/Reference Current section. In addition, a series resistor will introduce a temperature dependent offset error due to the input leakage current. A 1nA input leakage current will develop a 1ppm offset error on a 5k resistor if VREF = 5V. This error has a very strong temperature dependency. Output Data Format The LTC2420 serial output data stream is 24 bits long. The first 4 bits represent status information indicating the sign, input range and conversion state. The next 20 bits are the conversion result, MSB first. Bit 23 (first output bit) is the end of conversion (EOC) indicator. This bit is available at the SDO pin during the conversion and sleep states whenever the CS pin is LOW. This bit is HIGH during the conversion and goes LOW when the conversion is complete. Bit 22 (second output bit) is a dummy bit (DMY) and is always LOW. Bit 21 (third output bit) is the conversion result sign indicator (SIG). If VIN is >0, this bit is HIGH. If VIN is <0, this bit is LOW. The sign bit changes state during the zero code.
CS
BIT 23 SDO Hi-Z EOC
BIT 22 "0"
BIT 21 SIG
SCK
1 SLEEP
2
Figure 4. Output Data Timing
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Bit 20 (fourth output bit) is the extended input range (EXR) indicator. If the input is within the normal input range 0 VIN VREF, this bit is LOW. If the input is outside the normal input range, VIN > VREF or VIN < 0, this bit is HIGH. The function of these bits is summarized in Table 1.
Table 1. LTC2420 Status Bits
Input Range VIN > VREF 0 < VIN VREF VIN = 0+/0 - VIN < 0 Bit 23 EOC 0 0 0 0 Bit 22 DMY 0 0 0 0 Bit 21 SIG 1 1 1/0 0 Bit 20 EXR 1 0 0 1
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Bit 19 (fifth output bit) is the most significant bit (MSB). Bits 19-0 are the 20-bit conversion result MSB first. Bit 0 is the least significant bit (LSB). Data is shifted out of the SDO pin under control of the serial clock (SCK), see Figure 4. Whenever CS is HIGH, SDO remains high impedance and any SCK clock pulses are ignored by the internal data out shift register. In order to shift the conversion result out of the device, CS must first be driven LOW. EOC is seen at the SDO pin of the device once CS is pulled LOW. EOC changes real time from HIGH to LOW at the completion of a conversion. This signal may be used as an interrupt for an external microcontroller. Bit 23 (EOC) can be captured on the first rising edge of SCK. Bit 22 is shifted out of the device on the first falling edge of SCK. The final data bit (Bit 0) is shifted out on the falling edge of the 23rd SCK and may be latched on
BIT 20 EXT
BIT 19 MSB
BIT 4
BIT 0 LSB20
3
4
5
19
20
24 CONVERSION
2420 F04
DATA OUTPUT
LTC2420
APPLICATIO S I FOR ATIO
the rising edge of the 24th SCK pulse. On the falling edge of the 24th SCK pulse, SDO goes HIGH indicating a new conversion cycle has been initiated. This bit serves as EOC (Bit 23) for the next conversion cycle. Table 2 summarizes the output data format. As long as the voltage on the VIN pin is maintained within the - 0.3V to (VCC + 0.3V) absolute maximum operating range, a conversion result is generated for any input value from - 0.125 * VREF to 1.125 * VREF. For input voltages greater than 1.125 * VREF, the conversion result is clamped to the value corresponding to 1.125 * VREF. For input voltages below - 0.125 * VREF, the conversion result is clamped to the value corresponding to - 0.125 * VREF. Frequency Rejection Selection (FO Pin Connection) The LTC2420 internal oscillator provides better than 110dB normal mode rejection at the line frequency and its harmonics for 50Hz 2% or 60Hz 2%. For 60Hz rejection, FO (Pin 8) should be connected to GND (Pin 4) while for 50Hz rejection the FO pin should be connected to VCC (Pin 1). The selection of 50Hz or 60Hz rejection can also be made by driving FO to an appropriate logic level. A selection
Table 2. LTC2420 Output Data Format
Input Voltage VIN > 9/8 * VREF 9/8 * VREF VREF + 1LSB VREF 3/4VREF + 1LSB 3/4VREF 1/2VREF + 1LSB 1/2VREF 1/4VREF + 1LSB 1/4VREF 0+/0 - -1LSB -1/8 * VREF VIN < -1/8 * VREF Bit 23 EOC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 22 DMY 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 21 SIG 1 1 1 1 1 1 1 1 1 1 1/0* 0 0 0 Bit 20 EXR 1 1 1 0 0 0 0 0 0 0 0 1 1 1
*The sign bit changes state during the 0 code.
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change during the sleep or data output states will not disturb the converter operation. If the selection is made during the conversion state, the result of the conversion in progress may be outside specifications but the following conversions will not be affected. When a fundamental rejection frequency different from 50Hz or 60Hz is required or when the converter must be synchronized with an outside source, the LTC2420 can operate with an external conversion clock. The converter automatically detects the presence of an external clock signal at the FO pin and turns off the internal oscillator. The frequency fEOSC of the external signal must be at least 2560Hz (1Hz notch frequency) to be detected. The external clock signal duty cycle is not significant as long as the minimum and maximum specifications for the high and low periods tHEO and tLEO are observed. While operating with an external conversion clock of a frequency fEOSC, the LTC2420 provides better than 110dB normal mode rejection in a frequency range fEOSC/2560 4% and its harmonics. The normal mode rejection as a function of the input frequency deviation from fEOSC/2560 is shown in Figure 5.
Bit 19 MSB 0 0 0 1 1 1 1 0 0 0 0 1 1 1 Bit 18 0 0 0 1 1 0 0 1 1 0 0 1 1 1 Bit 17 0 0 0 1 0 1 0 1 0 1 0 1 1 1 Bit 16 1 1 0 1 0 1 0 1 0 1 0 1 0 0 Bit 15 1 1 0 1 0 1 0 1 0 1 0 1 0 0 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... Bit 0 LSB 1 1 0 1 0 1 0 1 0 1 0 1 0 0
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APPLICATIO S I FOR ATIO
-60 -70 -80 REJECTION (dB) -90 -100 -110 -120 -130 -140 -12 -8 -4 0 4 8 12 INPUT FREQUENCY DEVIATION FROM NOTCH FREQUENCY (%)
2420 F05
Figure 5. LTC2420 Normal Mode Rejection When Using an External Oscillator of Frequency fEOSC
Whenever an external clock is not present at the FO pin, the converter automatically activates its internal oscillator and enters the Internal Conversion Clock mode. The LTC2420 operation will not be disturbed if the change of conversion clock source occurs during the sleep state or during the data output state while the converter uses an external serial clock. If the change occurs during the conversion state, the result of the conversion in progress may be outside specifications but the following conversions will not be affected. If the change occurs during the data output state and the converter is in the Internal SCK mode, the serial clock duty cycle may be affected but the serial data stream will remain valid.
Table 3. LTC2420 State Duration
State CONVERT Operating Mode Internal Oscillator FO = LOW (60Hz Rejection) FO = HIGH (50Hz Rejection) External Oscillator
FO = External Oscillator with Frequency fEOSC kHz (fEOSC/2560 Rejection) FO = LOW/HIGH (Internal Oscillator) FO = External Oscillator with Frequency fEOSC kHz
SLEEP DATA OUTPUT Internal Serial Clock
External Serial Clock with Frequency fSCK kHz
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Table 3 summarizes the duration of each state as a function of FO. SERIAL INTERFACE The LTC2420 transmits the conversion results and receives the start of conversion command through a synchronous 3-wire interface. During the conversion and sleep states, this interface can be used to assess the converter status and during the data output state it is used to read the conversion result. Serial Clock Input/Output (SCK) The serial clock signal present on SCK (Pin 7) is used to synchronize the data transfer. Each bit of data is shifted out the SDO pin on the falling edge of the serial clock. In the Internal SCK mode of operation, the SCK pin is an output and the LTC2420 creates its own serial clock by dividing the internal conversion clock by 8. In the External SCK mode of operation, the SCK pin is used as input. The internal or external SCK mode is selected on power-up and then reselected every time a HIGH-to-LOW transition is detected at the CS pin. If SCK is HIGH or floating at powerup or during this transition, the converter enters the internal SCK mode. If SCK is LOW at power-up or during this transition, the converter enters the external SCK mode.
Duration 133ms 160ms 20510/fEOSCs As Long As CS = HIGH Until CS = 0 and SCK As Long As CS = LOW But Not Longer Than 1.26ms (24 SCK cycles) As Long As CS = LOW But Not Longer Than 256/fEOSCms (24 SCK cycles) As Long As CS = LOW But Not Longer Than 24/fSCKms (24 SCK cycles)
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LTC2420
APPLICATIO S I FOR ATIO
Serial Data Output (SDO) The serial data output pin, SDO (Pin 6), drives the serial data during the data output state. In addition, the SDO pin is used as an end of conversion indicator during the conversion and sleep states. When CS (Pin 5) is HIGH, the SDO driver is switched to a high impedance state. This allows sharing the serial interface with other devices. If CS is LOW during the convert or sleep state, SDO will output EOC. If CS is LOW during the conversion phase, the EOC bit appears HIGH on the SDO pin. Once the conversion is complete, EOC goes LOW. The device remains in the sleep state until the first rising edge of SCK occurs while CS is LOW. Chip Select Input (CS) The active LOW chip select, CS (Pin 5), is used to test the conversion status and to enable the data output transfer as described in the previous sections. In addition, the CS signal can be used to trigger a new conversion cycle before the entire serial data transfer has been completed. The LTC2420 will abort any serial data transfer in progress and start a new conversion cycle anytime a LOW-to-HIGH transition is detected at the CS pin after the converter has entered the data output state (i.e., after the first rising edge of SCK occurs while CS is LOW). Finally, CS can be used to control the free-running modes of operation, see Serial Interface Timing Modes section. Grounding CS will force the ADC to continuously convert at the maximum output rate selected by FO. Tying a capacitor to CS will reduce the output rate and power dissipation by a factor proportional to the capacitor's value, see Figures 13 to 15.
Table 4. LTC2420 Interface Timing Modes
SCK Source External External Internal Internal Internal Conversion Cycle Control CS and SCK SCK CS Continuous CEXT Data Output Control CS and SCK SCK CS Internal Internal Connection and Waveforms Figures 6, 7 Figure 8 Figures 9, 10 Figure 11 Figure 12
Configuration External SCK, Single Cycle Conversion External SCK, 2-Wire I/O Internal SCK, Single Cycle Conversion Internal SCK, 2-Wire I/O, Continuous Conversion Internal SCK, Autostart Conversion
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SERIAL INTERFACE TIMING MODES The LTC2420's 3-wire interface is SPI and MICROWIRE compatible. This interface offers several flexible modes of operation. These include internal/external serial clock, 2- or 3-wire I/O, single cycle conversion and autostart. The following sections describe each of these serial interface timing modes in detail. In all these cases, the converter can use the internal oscillator (FO = LOW or FO = HIGH) or an external oscillator connected to the FO pin. Refer to Table 4 for a summary. External Serial Clock, Single Cycle Operation (SPI/MICROWIRE Compatible) This timing mode uses an external serial clock to shift out the conversion result and a CS signal to monitor and control the state of the conversion cycle, see Figure 6. The serial clock mode is selected on the falling edge of CS. To select the external serial clock mode, the serial clock pin (SCK) must be LOW during each CS falling edge. The serial data output pin (SDO) is Hi-Z as long as CS is HIGH. At any time during the conversion cycle, CS may be pulled LOW in order to monitor the state of the converter. While CS is pulled LOW, EOC is output to the SDO pin. EOC = 1 while a conversion is in progress and EOC = 0 if the device is in the sleep state. Independent of CS, the device automatically enters the low power sleep state once the conversion is complete. When the device is in the sleep state (EOC = 0), its conversion result is held in an internal static shift register. The device remains in the sleep state until the first rising edge of SCK is seen while CS is LOW. Data is shifted out the SDO pin on each falling edge of SCK. This enables
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LTC2420
APPLICATIO S I FOR ATIO U
2.7V TO 5.5V 1F VCC LTC2420 VREF 0.1V TO VCC VIN -0.12VREF TO 1.12VREF VREF SCK FO
VCC
CS TEST EOC SDO Hi-Z Hi-Z TEST EOC TEST EOC
BIT 23 EOC
SCK (EXTERNAL) CONVERSION SLEEP DATA OUTPUT CONVERSION
2420 F06
Figure 6. External Serial Clock, Single Cycle Operation
external circuitry to latch the output on the rising edge of SCK. EOC can be latched on the first rising edge of SCK and the last bit of the conversion result can be latched on the 24th rising edge of SCK. On the 24th falling edge of SCK, the device begins a new conversion. SDO goes HIGH (EOC = 1) indicating a conversion is in progress. At the conclusion of the data cycle, CS may remain LOW and EOC monitored as an end-of-conversion interrupt. Alternatively, CS may be driven HIGH setting SDO to Hi-Z. As described above, CS may be pulled LOW at any time in order to monitor the conversion status. Typically, CS remains LOW during the data output state. However, the data output state may be aborted by pulling CS HIGH anytime between the first rising edge and the 24th falling edge of SCK, see Figure 7. On the rising edge of CS, the device aborts the data output state and immediately initiates a new conversion. This is useful for systems not requiring all 24 bits of output data, aborting an invalid conversion cycle or synchronizing the start of a conversion.
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= 50Hz REJECTION = EXTERNAL OSCILLATOR = 60Hz REJECTION
VIN GND
SDO CS
BIT 22
BIT 21 SIG
BIT 20 EXR
BIT 19 MSB
BIT 18
BIT 4
BIT 0 LSB20
Hi-Z
External Serial Clock, 2-Wire I/O This timing mode utilizes a 2-wire serial I/O interface. The conversion result is shifted out of the device by an externally generated serial clock (SCK) signal, see Figure 8. CS may be permanently tied to ground (Pin 4), simplifying the user interface or isolation barrier. The external serial clock mode is selected at the end of the power-on reset (POR) cycle. The POR cycle is concluded approximately 0.5ms after VCC exceeds 2.2V. The level applied to SCK at this time determines if SCK is internal or external. SCK must be driven LOW prior to the end of POR in order to enter the external serial clock timing mode. Since CS is tied LOW, the end-of-conversion (EOC) can be continuously monitored at the SDO pin during the convert and sleep states. EOC may be used as an interrupt to an external controller indicating the conversion result is ready. EOC = 1 while the conversion is in progress and EOC = 0 once the conversion enters the low power sleep state. On the falling edge of EOC, the conversion result is loaded
LTC2420
APPLICATIO S I FOR ATIO U
2.7V TO 5.5V 1F VCC LTC2420 VREF 0.1V TO VCC VIN -0.12VREF TO 1.12VREF VREF SCK FO
VCC
CS TEST EOC TEST EOC TEST EOC
BIT 0 SDO EOC
Hi-Z
SCK (EXTERNAL) SLEEP CONVERSION DATA OUTPUT SLEEP DATA OUTPUT CONVERSION
2420 F07
Figure 7. External Serial Clock, Reduced Data Output Length
CS
SDO
SCK (EXTERNAL) CONVERSION SLEEP DATA OUTPUT CONVERSION
2420 F07
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Hi-Z
EOC
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= 50Hz REJECTION = EXTERNAL OSCILLATOR = 60Hz REJECTION
VIN GND
SDO CS
BIT 23 EOC Hi-Z
BIT 22
BIT 21 SIG
BIT 20 EXR
BIT 19 MSB
BIT 9
BIT 8
Hi-Z
2.7V TO 5.5V 1F VCC LTC2420 VREF 0.1V TO VCC VIN -0.12VREF TO 1.12VREF VREF SCK FO
VCC
= 50Hz REJECTION = EXTERNAL OSCILLATOR = 60Hz REJECTION
VIN GND
SDO CS
BIT 23
BIT 22
BIT 21 SIG
BIT 20 EXR
BIT 19 MSB
BIT 18
BIT 4
BIT 0 LSB20
Figure 8. External Serial Clock, CS = 0 Operation
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LTC2420
APPLICATIO S I FOR ATIO
into an internal static shift register. The device remains in the sleep state until the first rising edge of SCK. Data is shifted out the SDO pin on each falling edge of SCK enabling external circuitry to latch data on the rising edge of SCK. EOC can be latched on the first rising edge of SCK. On the 24th falling edge of SCK, SDO goes HIGH (EOC = 1) indicating a new conversion has begun. Internal Serial Clock, Single Cycle Operation This timing mode uses an internal serial clock to shift out the conversion result and a CS signal to monitor and control the state of the conversion cycle, see Figure 9. In order to select the internal serial clock timing mode, the serial clock pin (SCK) must be floating (Hi-Z) or pulled HIGH prior to the falling edge of CS. The device will not enter the internal serial clock mode if SCK is driven LOW on the falling edge of CS. An internal weak pull-up resistor is active on the SCK pin during the falling edge of CS; therefore, the internal serial clock timing mode is automatically selected if SCK is not externally driven. The serial data output pin (SDO) is Hi-Z as long as CS is HIGH. At any time during the conversion cycle, CS may be pulled LOW in order to monitor the state of the converter. Once CS is pulled LOW, SCK goes LOW and EOC is output
2.7V TO 5.5V 1F VCC LTC2420 VREF 0.1V TO VCC VIN -0.12VREF TO 1.12VREF VREF SCK FO
VCC
BIT 23 EOC
BIT 22
SCK (INTERNAL) CONVERSION SLEEP DATA OUTPUT CONVERSION
2420 F09
Figure 9. Internal Serial Clock, Single Cycle Operation
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to the SDO pin. EOC = 1 while a conversion is in progress and EOC = 0 if the device is in the sleep state. When testing EOC, if the conversion is complete (EOC = 0), the device will exit the sleep state and enter the data output state if CS remains LOW. In order to prevent the device from exiting the low power sleep state, CS must be pulled HIGH before the first rising edge of SCK. In the internal SCK timing mode, SCK goes HIGH and the device begins outputting data at time tEOCtest after the falling edge of CS (if EOC = 0) or tEOCtest after EOC goes LOW (if CS is LOW during the falling edge of EOC). The value of tEOCtest is 23s if the device is using its internal oscillator (F0 = logic LOW or HIGH). If FO is driven by an external oscillator of frequency fEOSC, then tEOCtest is 3.6/fEOSC. If CS is pulled HIGH before time tEOCtest, the device remains in the sleep state. The conversion result is held in the internal static shift register. If CS remains LOW longer than tEOCtest, the first rising edge of SCK will occur and the conversion result is serially shifted out of the SDO pin. The data output cycle begins on this first rising edge of SCK and concludes after the 24th rising edge. Data is shifted out the SDO pin on each falling edge of SCK. The internally generated serial clock is output to the SCK pin. This signal may be used to shift the
VCC = 50Hz REJECTION = EXTERNAL OSCILLATOR = 60Hz REJECTION 10k VIN GND SDO CS BIT 21 SIG BIT 20 EXR BIT 19 MSB BIT 18 BIT 4 BIT 0 LSB20 Hi-Z Hi-Z
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LTC2420
APPLICATIO S I FOR ATIO
conversion result into external circuitry. EOC can be latched on the first rising edge of SCK and the last bit of the conversion result on the 24th rising edge of SCK. After the 24th rising edge, SDO goes HIGH (EOC = 1), SCK stays HIGH, and a new conversion starts. Typically, CS remains LOW during the data output state. However, the data output state may be aborted by pulling CS HIGH anytime between the first and 24th rising edge of SCK, see Figure 10. On the rising edge of CS, the device aborts the data output state and immediately initiates a new conversion. This is useful for systems not requiring all 24 bits of output data, aborting an invalid conversion cycle, or synchronizing the start of a conversion. If CS is pulled HIGH while the converter is driving SCK LOW, the internal pull-up is not available to restore SCK to a logic HIGH state. This will cause the device to exit the internal serial clock mode on the next falling edge of CS. This can be avoided by adding an external 10k pull-up resistor to the SCK pin or by never pulling CS HIGH when SCK is LOW. Whenever SCK is LOW, the LTC2420's internal pull-up at pin SCK is disabled. Normally, SCK is not externally driven
2.7V TO 5.5V 1F VCC LTC2420 VREF 0.1V TO VCC VIN -0.12VREF TO 1.12VREF VREF SCK FO
VCC
> tEOCtest CS TEST EOC TEST EOC
BIT 0 SDO Hi-Z EOC Hi-Z
Hi-Z
Hi-Z
SCK (INTERNAL) SLEEP CONVERSION DATA OUTPUT SLEEP DATA OUTPUT CONVERSION
2420 F10
Figure 10. Internal Serial Clock, Reduced Data Output Length
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if the device is in the internal SCK timing mode. However, certain applications may require an external driver on SCK. If this driver goes Hi-Z after outputting a LOW signal, the LTC2420's internal pull-up remains disabled. Hence, SCK remains LOW. On the next falling edge of CS, the device is switched to the external SCK timing mode. By adding an external 10k pull-up resistor to SCK, this pin goes HIGH once the external driver goes Hi-Z. On the next CS falling edge, the device will remain in the internal SCK timing mode. A similar situation may occur during the sleep state when CS is pulsed HIGH-LOW-HIGH in order to test the conversion status. If the device is in the sleep state (EOC = 0), SCK will go LOW. Once CS goes HIGH (within the time period defined above as tEOCtest), the internal pull-up is activated. For a heavy capacitive load on the SCK pin, the internal pull-up may not be adequate to return SCK to a HIGH level before CS goes low again. This is not a concern under normal conditions where CS remains LOW after detecting EOC = 0. This situation is easily overcome by adding an external 10k pull-up resistor to the SCK pin.
VCC = 50Hz REJECTION = EXTERNAL OSCILLATOR = 60Hz REJECTION 10k VIN GND SDO CS BIT 23 EOC BIT 22 BIT 21 SIG BIT 20 EXR BIT 19 MSB Hi-Z BIT 18 BIT 8 TEST EOC
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APPLICATIO S I FOR ATIO
Internal Serial Clock, 2-Wire I/O, Continuous Conversion This timing mode uses a 2-wire, all output (SCK and SDO) interface. The conversion result is shifted out of the device by an internally generated serial clock (SCK) signal, see Figure 11. CS may be permanently tied to ground (Pin 4), simplifying the user interface or isolation barrier. The internal serial clock mode is selected at the end of the power-on reset (POR) cycle. The POR cycle is concluded approximately 0.5ms after VCC exceeds 2.2V. An internal weak pull-up is active during the POR cycle; therefore, the internal serial clock timing mode is automatically selected if SCK is not externally driven LOW (if SCK is loaded such that the internal pull-up cannot pull the pin HIGH, the external SCK mode will be selected). During the conversion, the SCK and the serial data output pin (SDO) are HIGH (EOC = 1). Once the conversion is complete, SCK and SDO go LOW (EOC = 0) indicating the conversion has finished and the device has entered the low power sleep state. The part remains in the sleep state a minimum amount of time (1/2 the internal SCK period)
2.7V TO 5.5V 1F VCC LTC2420 VREF 0.1V TO VCC VIN -0.12VREF TO 1.12VREF VREF SCK FO
VCC
CS
SDO
BIT 23 EOC
BIT 22
BIT 21 SIG
SCK (INTERNAL) CONVERSION SLEEP DATA OUTPUT CONVERSION
2420 F11
Figure 11. Internal Serial Clock, Continuous Operation
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then immediately begins outputting data. The data output cycle begins on the first rising edge of SCK and ends after the 24th rising edge. Data is shifted out the SDO pin on each falling edge of SCK. The internally generated serial clock is output to the SCK pin. This signal may be used to shift the conversion result into external circuitry. EOC can be latched on the first rising edge of SCK and the last bit of the conversion result can be latched on the 24th rising edge of SCK. After the 24th rising edge, SDO goes HIGH (EOC = 1) indicating a new conversion is in progress. SCK remains HIGH during the conversion. Internal Serial Clock, Autostart Conversion This timing mode is identical to the internal serial clock, 2-wire I/O described above with one additional feature. Instead of grounding CS, an external timing capacitor is tied to CS. While the conversion is in progress, the CS pin is held HIGH by an internal weak pull-up. Once the conversion is complete, the device enters the low power sleep state and an internal 25nA current source begins discharging the
= 50Hz REJECTION = EXTERNAL OSCILLATOR = 60Hz REJECTION VIN GND SDO CS BIT 20 EXR BIT 19 MSB BIT 18 BIT 4 BIT 0 LSB20
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LTC2420
APPLICATIO S I FOR ATIO
capacitor tied to CS, see Figure 12. The time the converter spends in the sleep state is determined by the value of the external timing capacitor, see Figures 13 and 14. Once the voltage at CS falls below an internal threshold (1.4V), the device automatically begins outputting data. The data output cycle begins on the first rising edge of SCK and ends on the 24th rising edge. Data is shifted out the SDO pin on each falling edge of SCK. The internally generated serial clock is output to the SCK pin. This signal may be used to shift the conversion result into external circuitry. After the 24th rising edge, CS is pulled HIGH and a new conversion is immediately started. This is useful in applications requiring periodic monitoring and ultralow power. Figure 15 shows the average supply current as a function of capacitance on CS. It should be noticed that the external capacitor discharge current is kept very small in order to decrease the converter power dissipation in the sleep state. In the autostart mode the analog voltage on the CS pin cannot be observed
tSAMPLE (SEC)
VREF 0.1V TO VCC VIN -0.12VREF TO 1.12VREF
VCC CS GND BIT 23 SDO Hi-Z EOC BIT 22 BIT 21 SIG Hi-Z BIT 0
SCK (INTERNAL) CONVERSION SLEEP DATA OUTPUT CONVERSION
2420 F12
Figure 12. Internal Serial Clock, Autostart Operation
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without disturbing the converter operation using a regular oscilloscope probe. When using this configuration, it is important to minimize the external leakage current at the CS pin by using a low leakage external capacitor and properly cleaning the PCB surface.
7 6 5 4 3 2 VCC = 5V 1 0 1 10 VCC = 3V 100 1000 10000 CAPACITANCE ON CS (pF) 100000
2420 F13
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Figure 13. CS Capacitance vs fSAMPLE
2.7V TO 5.5V 1F VCC LTC2420 VREF SCK FO
VCC
= 50Hz REJECTION = EXTERNAL OSCILLATOR = 60Hz REJECTION
VIN GND
SDO CS CEXT
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LTC2420
APPLICATIO S I FOR ATIO
8 7 6
SAMPLE RATE (Hz)
5 4 3 2 1 0 0 10
VCC = 5V VCC = 3V
100 10000 100000 1000 CAPACITANCE ON CS (pF)
2420 F14
Figure 14. CS Capacitance vs Output Rate
300 250
SUPPLY CURRENT (ARMS)
VCC = 5V
200 VCC = 3V 150 100 50 0 1 10 100 1000 10000 CAPACITANCE ON CS (pF) 100000
2420 F15
Figure 15. CS Capacitance vs Supply Current
The internal serial clock mode is selected every time the voltage on the CS pin crosses an internal threshold voltage. An internal weak pull-up at the SCK pin is active while CS is discharging; therefore, the internal serial clock timing mode is automatically selected if SCK is floating. It is important to ensure there are no external drivers pulling SCK LOW while CS is discharging. DIGITAL SIGNAL LEVELS The LTC2420's digital interface is easy to use. Its digital inputs (FO, CS and SCK in External SCK mode of operation) accept standard TTL/CMOS logic levels and the internal hysteresis receivers can tolerate edge rates as slow as 100s. However, some considerations are required to take advantage of exceptional accuracy and low supply current.
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The digital output signals (SDO and SCK in Internal SCK mode of operation) are less of a concern because they are not generally active during the conversion state. In order to preserve the LTC2420's accuracy, it is very important to minimize the ground path impedance which may appear in series with the input and/or reference signal and to reduce the current which may flow through this path. The GND pin should be connected to a low resistance ground plane through a minimum length trace. The use of multiple via holes is recommended to further reduce the connection resistance. The LTC2420's power supply current flowing through the 0.01 resistance of the common ground pin will develop a 2.5V offset signal. For a reference voltage VREF = 2.5V, this represents a 1ppm offset error. In an alternative configuration, the GND pin of the converter can be the single-point-ground in a single point grounding system. The input signal ground, the reference signal ground, the digital drivers ground (usually the digital ground) and the power supply ground (the analog ground) should be connected in a star configuration with the common point located as close to the GND pin as possible. The power supply current during the conversion state should be kept to a minimum. This is achieved by restricting the number of digital signal transitions occurring during this period. While a digital input signal is in the range 0.5V to (VCC - 0.5V), the CMOS input receiver draws additional current from the power supply. It should be noted that, when any one of the digital input signals (FO, CS and SCK in External SCK mode of operation) is within this range, the LTC2420 power supply current may increase even if the signal in question is at a valid logic level. For micropower operation and in order to minimize the potential errors due to additional ground pin current, it is recommended to drive all digital input signals to full CMOS levels [VIL < 0.4V and VOH > (VCC - 0.4V)]. Severe ground pin current disturbances can also occur due to the undershoot of fast digital input signals. Undershoot and overshoot can occur because of the impedance mismatch at the converter pin when the transition time of an external control signal is less than twice the
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LTC2420
APPLICATIO S I FOR ATIO
propagation delay from the driver to LTC2420. For reference, on a regular FR-4 board, signal propagation velocity is approximately 183ps/inch for internal traces and 170ps/inch for surface traces. Thus, a driver generating a control signal with a minimum transition time of 1ns must be connected to the converter pin through a trace shorter than 2.5 inches. This problem becomes particularly difficult when shared control lines are used and multiple reflections may occur. The solution is to carefully terminate all transmission lines close to their characteristic impedance. Parallel termination near the LTC2420 pin will eliminate this problem but will increase the driver power dissipation. A series resistor between 27 and 56 placed near the driver or near the LTC2420 pin will also eliminate this problem without additional power dissipation. The actual resistor value depends upon the trace impedance and connection topology. Driving the Input and Reference The analog input and reference of the typical delta-sigma analog-to-digital converter are applied to a switched capacitor network. This network consists of capacitors switching between the analog input (VIN), ground (Pin 4) and the reference (VREF). The result is small current spikes seen at both VIN and VREF. A simplified input equivalent circuit is shown in Figure 16. The key to understanding the effects of this dynamic input current is based on a simple first order RC time constant model. Using the internal oscillator, the LTC2420's internal switched capacitor network is clocked at 153,600Hz
VCC IREF(LEAK) VREF IREF(LEAK) IIN VIN IIN(LEAK) RSW 5k GND
2420 F16
RSW 5k
VCC IIN(LEAK) RSW 5k AVERAGE INPUT CURRENT: IIN = 0.25(VIN - 0.5 * VREF)fCEQ CEQ 1pF (TYP)
INTPUT SIGNAL SOURCE
SWITCHING FREQUENCY f = 153.6kHz FOR INTERNAL OSCILLATOR (fO = LOGIC LOW OR HIGH) f = fEOSC FOR EXTERNAL OSCILLATORS
Figure 16. LTC2420 Equivalent Analog Input Circuit
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corresponding to a 6.5s sampling period. Fourteen time constants are required each time a capacitor is switched in order to achieve 1ppm settling accuracy. Therefore, the equivalent time constant at VIN and VREF should be less than 6.5s/14 = 460ns in order to achieve 1ppm accuracy. Input Current (VIN) If complete settling occurs on the input, conversion results will be uneffected by the dynamic input current. If the settling is incomplete, it does not degrade the linearity performance of the device. It simply results in an offset/ full-scale shift, see Figure 17. To simplify the analysis of input dynamic current, two separate cases are assumed: large capacitance at VIN (CIN > 0.01F) and small capacitance at VIN (CIN < 0.01F). If the total capacitance at VIN (see Figure 18) is small (< 0.01F), relatively large external source resistances (up to 80k for 20pF parasitic capacitance) can be tolerated without any offset/full-scale error. Figures 19 and 20 show a family of offset and full-scale error curves for various small valued input capacitors (CIN < 0.01F) as a function of input source resistance.
TUE 0 VREF/2 VIN VREF
2420 F17
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Figure 17. Offset/Full-Scale Shift
RSOURCE VIN CIN CPAR 20pF LTC2420
2420 F18
Figure 18. An RC Network at VIN
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LTC2420
APPLICATIO S I FOR ATIO
50 40 VCC = 5V VREF = 5V VIN = 0V TA = 25C
OFFSET ERROR (ppm)
OFFSET ERROR (ppm)
30
20
CIN = 0pF CIN = 100pF CIN = 1000pF CIN = 0.01F
10 5 0 0 1 10 1k 100 RSOURCE () 10k 100k
2420 F19
Figure 19. Offset vs RSOURCE (Small C)
10 0 FULL-SCALE ERROR (ppm) FULL-SCALE ERROR (ppm) -10 -20 -30 -40 -50 1 VCC = 5V VREF = 5V VIN = 5V TA = 25C 10 CIN = 0.01F CIN = 0pF CIN = 100pF CIN = 1000pF
100 1k RSOURCE ()
10k
100k
2420 F20
Figure 20. Full-Scale Error vs RSOURCE (Small C)
For large input capacitor values (CIN > 0.01F), the input spikes are averaged by the capacitor into a DC current. The gain shift becomes a linear function of input source resistance independent of input capacitance, see Figures 21 and 22. The equivalent input impedance is 16.6M. This results in 150nA of input dynamic current at the extreme values of VIN (VIN = 0V and VIN = VREF, when VREF = 5V). This corresponds to a 0.3ppm shift in offset and full-scale readings for every 10 of input source resistance. In addition to the input current spikes, the input ESD protection diodes have a temperature dependent leakage current. This leakage current, nominally 1nA (10nA max), results in a fixed offset shift of 10V for a 10k source resistance.
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35 30 25 CIN = 22F CIN = 10F CIN = 1F CIN = 0.1F CIN = 0.01F CIN = 0.001F 20 VCC = 5V VREF = 5V 15 VIN = 0V TA = 25C 10 0 200 400 600 RSOURCE () 800 1000
2420 F21
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Figure 21. Offset vs RSOURCE (Large C)
5 0 -5 -10 -15 -20 -25 -30 -35 0 CIN = 22F CIN = 10F CIN = 1F CIN = 0.1F CIN = 0.01F CIN = 0.001F 200 400 600 RSOURCE () 800 1000
2420 F22
VCC = 5V VREF = 5V VIN = 0V TA = 25C
Figure 22. Full-Scale Error vs RSOURCE (Large C)
Reference Current (VREF) Similar to the analog input, the reference input has a dynamic input current. This current has negligible effect on the offset. However, the reference current at VIN = VREF is similar to the input current at full-scale. For large values of reference capacitance (CVREF > 0.01F), the full-scale error shift is 0.03ppm/ of external reference resistance independent of the capacitance at VREF, see Figure 23. If the capacitance tied to VREF is small (CVREF < 0.01F), an input resistance of up to 80k (20pF parasitic capacitance at VREF) may be tolerated, see Figure 24. Unlike the analog input, the integral nonlinearity of the device can be degraded with excessive external RC time constants tied to the reference input. If the capacitance at
LTC2420
APPLICATIO S I FOR ATIO
60 50
FULL-SCALE ERROR (ppm)
INL ERROR (ppm)
40
CVREF = 22F CVREF = 10F CVREF = 1F CVREF = 0.1F CVREF = 0.01F CVREF = 0.001F
30 VCC = 5V VREF = 5V 20 VIN = 5V TA = 25C 10 0 -10 0 200 600 800 RESISTANCE AT VREF () 400 1000
2420 F23
Figure 23. Full-Scale Error vs RVREF (Large C)
500 VCC = 5V = 5V V 400 VREF 5V IN = TA = 25C 300
CVREF = 1000pF CVREF = 100pF
INL ERROR (ppm)
VOLTAGE
200 CVREF = 0.01F 100 0 -100 -200 1 10 100 1k 10k RESISTANCE AT VREF () 100k
2420 F24
CVREF = 0pF
Figure 24. Full-Scale Error vs RVREF (Small C)
node VREF is small (CVREF < 0.01F), the reference input can tolerate large external resistances without reduction in INL, see Figure 25. If the external capacitance is large (CVREF > 0.01F), the linearity will be degraded by 0.015ppm/ independent of capacitance at VREF, see Figure 26. In addition to the dynamic reference current, the VREF ESD protection diodes have a temperature dependent leakage current. This leakage current, nominally 1nA (10nA max), results in a fixed full-scale shift of 10V for a 10k source resistance.
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50 VCC = 5V V = 5V 40 T REF 25C A= 30 CVREF = 1000pF 20 CVREF = 100pF 10 CVREF = 0.01F 0 -10 -20 1 10 100 1k 10k RESISTANCE AT VREF () 100k
2420 F25
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CVREF = 0pF
Figure 25. INL Error vs RVREF (Small C)
10 8 6 4 2 0 -2 -4 -6 -8 -10 0 200 400 600 800 RESISTANCE AT VREF () 1000
2420 F26
CVREF = 22F CVREF = 10F CVREF = 1F CVREF = 0.1F CVREF = 0.01F CVREF = 0.001F VCC = 5V VREF = 5V TA = 25C
Figure 26. INL Error vs RVREF (Large C)
ANTIALIASING One of the advantages delta-sigma ADCs offer over conventional ADCs is on-chip digital filtering. Combined with a large oversampling ratio, the LTC2420 significantly simplifies antialiasing filter requirements. The digital filter provides very high rejection except at integer multiples of the modulator sampling frequency (fS), see Figure 27. The modulator sampling frequency is 256 * FO, where FO is the notch frequency (typically 50Hz or 60Hz). The bandwidth of signals not rejected by the digital filter is narrow ( 0.2%) compared to the bandwidth of the frequencies rejected.
25
LTC2420
APPLICATIO S I FOR ATIO
0 -20 -40
REJECTION (dB)
-60 -80 -100 -120
-140 0 fS/2 INPUT FREQUENCY
2420 F27
fS 256 VREF = 5V 12 BITS
Figure 27. Sinc4 Filter Rejection
TOTAL UNADJUSTED ERROR (ppm)
As a result of the oversampling ratio (256) and the digital filter, minimal (if any) antialias filtering is required in front of the LTC2420. If passive RC components are placed in front of the LTC2420 the input dynamic current should be considered (see Input Current section). In cases where large effective RC time constants are used, an external buffer amplifier may be required to minimize the effects of input dynamic current. The modulator contained within the LTC2420 can handle large-signal level perturbations without saturating. Signal levels up to 40% of VREF do not saturate the analog modulator. These signals are limited by the input ESD protection to 300mV below ground and 300mV above VCC. Operation at Higher Data Output Rates The LTC2420 typically operates with an internal oscillator of 153.6kHz. This corresponds to a notch frequency of 60Hz and an output rate of 7.5 samples/second. The internal oscillator is enabled if the FO pin is logic LOW (logic HIGH for a 50Hz notch). It is possible to drive the FO pin with an external oscillator for higher data output rates. As shown in Figure 28, an external clock of 2.048MHz applied to the FO pin results in a notch frequency of 800Hz with a data output rate of 100 samples/second. Figure 29 shows the total unadjusted error (Offset Error + Full-Scale Error + INL + DNL) as a function of the output data rate with a 5V reference. The relationship between the
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800Hz NOTCH (100 SAMPLES/SECOND) 60Hz NOTCH (7.5 SAMPLES/SECOND) 1 2 3 4 LTC2420 VCC VREF VIN GND FO SCK SDO CS 8 7 6 5 EXTERNAL 2.048MHz CLOCK SOURCE
2420 F28
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INTERNAL 153.6kHz OSCILLATOR
Figure 28. Selectable 100 Samples/Second Turbo Mode
224 192 160 128 96 14 BITS 64 32 0 0 50 100 16 BITS 150
2420 F29
13 BITS
OUTPUT RATE (SAMPLES/SEC)
Figure 29. Total Error vs Output Rate (VREF = 5V)
output data rate (ODR) and the frequency applied to the FO pin (FO) is: ODR = FO/20480 For output data rates up to 50 samples/second, the total unadjusted error (TUE) is better than 16 bits, and better than 12 bits at 100 samples/second. As shown in Figure 30, for output data rates of 100 samples/second, the TUE is better than 15 bits for VREF below 2.5V. Figure 31 shows an unaveraged total unadjusted error for the LTC2420 operating at 100 samples/second with VREF = 2.5V. Figure 32 shows the same device operating with a 5V reference and an output data rate of 7.5 samples/second. At 100 samples/second, the LTC2420 can be used to capture transient data. This is useful for monitoring settling or auto gain ranging in a system. The LTC2420 can monitor signals at an output rate of 100 samples/second.
LTC2420
APPLICATIO S I FOR ATIO
256 OUTPUT RATE = 100sps
TOTAL UNADJUSTED ERROR (ppm)
224 192 160 128 96 64 32 0 1.0 1.5 14 BITS 15 BITS 13 BITS
Figure 30. Total Error vs VREF (Output Rate = 100sps)
10 TOTAL UNADJUSTED ERROR (ppm) 5 0 -5 -10 -15 -20 -25 -30 -35 -40 0 INPUT VOLTAGE (V)
TOTAL UNADJUSTED ERROR (ppm)
VCC = 5V VREF = 2.5V
2.5
2420 F31
Figure 31. Total Unadjusted Error at 100 Samples/Second (No Averaging)
After acquiring 100 samples/second data the FO pin may be driven LOW enabling 60Hz rejection to 110dB and the highest possible DC accuracy. The no latency architecture of the LTC2420 allows consecutive readings (one at 100 samples/second the next at 7.5 samples/second) without interaction between the two readings.
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12 BITS 2.0 2.5 3.0 3.5 4.0 REFERENCE VOLTAGE (V) 4.5 5.0
2420 F30
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6 4 2 0 -2 -4 -6 -8 -10 0 INPUT VOLTAGE (V)
VCC = 5V VREF = 5V
5
2420 F32
Figure 32. Total Unadjusted Error at 7.5 Samples/Second (No Averaging)
As shown in Figure 33, the LTC2420 can capture transient data with 90dB of dynamic range (with a 300mVP-P input signal at 2Hz). The exceptional DC performance of the LTC2420 enables signals to be digitized independent of a large DC offset. Figures 34a and 34b show the dynamic performance with a 15Hz signal superimposed on a 2V DC level. The same signal with no DC level is shown in Figures 34c and 34d.
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LTC2420
APPLICATIO S I FOR ATIO
0.20
ADC OUTPUT (NORMALIZED TO VOLTS)
500ms 0.15 0.10
fIN = 2Hz
MAGNITUDE (dB)
0.05 0 -0.05 -0.10 -0.15 -0.20 TIME
2420 F33a
33a. Digitized Waveform Figure 33. Transient Signal Acquisiton
2.20
ADC OUTPUT (NORMALIZED TO VOLTS)
VIN = 300mVP-P + 2V DC
2.15 2.10
MAGNITUDE (dB)
2.05 2.00 1.95 1.90 1.85 1.80 TIME
2420 F34a
34a. Digitized Waveform with 2V DC Offset
0.20
ADC OUTPUT (NORMALIZED TO VOLTS)
VIN = 300mVP-P + 0V DC
0.15 0.10
MAGNITUDE (dB)
0.05 0.00 -0.05 -0.10 -0.15 -0.20 TIME
2420 F34c
34c. Digitized Waveform with No Offset
Figure 34. Using the LTC2420's High Accuracy Wide Dynamic Range to Digitize a 300mVP-P 15Hz Waveform with a Large DC Offset (VCC = 5V, VREF = 5V)
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0 -20 -40 -60 -80 2Hz 100sps 0V OFFSET -100 -120 FREQUENCY (Hz)
2420 F33b
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33b. Output FFT
0 -20 -40 -60 -80
15Hz 100sps 2V OFFSET
-100 -120 FREQUENCY (Hz)
2420 F34b
34b. FFT Waveform with 2V DC Offset
0 -20 -40 -60 -80 15Hz 100sps 0V OFFSET
-100 -120 FREQUENCY (Hz)
2420 F34d
34d. FFT Waveform with No Offset
LTC2420
TYPICAL APPLICATIO S
SYNCHRONIZATION OF MULTIPLE LTC2420s Since the LTC2420's absolute accuracy (total unadjusted error) is 10ppm, applications utilizing multiple matched ADCs are possible. Simultaneous Sampling with Two LTC2420s One such application is synchronizing multiple LTC2420s, see Figure 35. The start of conversion is synchronized to the rising edge of CS. In order to synchronize multiple LTC2420s, CS is a common input to all the ADCs. To prevent the converters from autostarting a new conversion at the end of data output read, 23 or fewer SCK clock signals are applied to the LTC2420 instead of 24 (the 24th falling edge would start a conversion). The exact timing and frequency for the SCK signal is not critical since it is only shifting out the data. In this case, two LTC2420's simultaneously start and end their conversion cycles under the external control of CS. Increasing the Output Rate Using Multiple LTC2420s A second application uses multiple LTC2420s to increase the effective output rate by 4x, see Figure 36. In this case, four LTC2420s are interleaved under the control of separate CS signals. This increases the effective output rate from 7.5Hz to 30Hz (up to a maximum of 400Hz). Additionally, the one-shot output spectrum is unfolded allowing further digital signal processing of the conversion results. SCK and SDO may be common to all four LTC2420s. The four CS rising edges equally divide one LTC2420 conversion cycle (7.5Hz for 60Hz notch frequency). In order to synchronize the start of conversion to CS, 23 or less SCK clock pulses must be applied to each ADC. Both the synchronous and 4x output rate applications use the external serial clock and single cycle operation with reduced data output length (see Serial Interface Timing Modes section and Figure 7). An external oscillator clock is applied commonly to the FO pin of each LTC2420 in order to synchronize the sampling times. Both circuits may be extended to include more LTC2420s.
CONTROLLER
CS
SCK1 23 OR LESS CLOCK CYCLES SCK2 23 OR LESS CLOCK CYCLES SDO1
SDO2
2420 F35
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SCK2 SCK1 LTC2420 #1 VCC VREF VIN GND CS SDO1 SDO2 VREF (0.1V TO VCC) FO SCK SDO CS LTC2420 #2 VCC VREF VIN GND FO SCK SDO CS EXTERNAL OSCILLATOR (153,600HZ)
Figure 35. Synchronous Conversion--Extendable
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LTC2420
TYPICAL APPLICATIO S
LTC2420 #1 VCC VREF VIN CONTROLLER SCK SDO CS1 CS2 CS3 CS4 GND FO SCK SDO CS LTC2420 #2 VCC VREF VIN GND FO SCK SDO CS LTC2420 #3 VCC VREF VIN GND FO SCK SDO CS LTC2420 #4 VCC VREF VIN GND FO SCK SDO CS VREF (0.1V TO VCC) EXTERNAL OSCILLATOR (153,600HZ)
CS1
CS2
CS3
CS4 23 OR LESS CLOCK PULSES
SCK
SDO
2420 F36
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Figure 36. 4x Output Rate LTC2420 System
LTC2420
TYPICAL APPLICATIO S
Single-Chip Instrumentation Amplifier for the LTC2420 The circuit in Figure 37 is a simple solution for processing differential signals in pressure transducer, weigh scale or strain gauge applications that can operate on a supply voltage range of 5V to 15V. The circuit uses an LT(R)1920 single-chip instrumentation amplifier to perform a differential to single-ended conversion. The amplifier's output voltage is applied to the LTC2420's input and converted to a digital value with an overall accuracy exceeding 17 bits (0.0008%). Key circuit performance results are shown in Table 5. The practical gain range for this topology as shown is from 5 to 100 because the LTC2420's wide dynamic range makes gains below 5 virtually unnecessary, whereas gains up to 100 significantly reduce the input referred noise. The optional passive RC lowpass filter between the amplifier's output and the LTC2420's input attenuates high frequency noise and its effects. Typically, the filter reduces the magnitude of averaged noise by 30% and improves resolution by 0.5 bit without compromising linearity. Resistor R2 performs two functions: it isolates C1 from the LTC2420's input and limits the LTC2420's input current should its input voltage drop below -300mV or swing above VCC + 300mV. The LT1920 is the choice for applications where low cost is important. For applications where more precision is required, the LT1167 is a pin-to-pin alternative choice with a lower offset voltage, lower input bias current and higher gain accuracy than the LT1920. The LT1920's maximum total input-referred offset (VOST) is 135V for a gain of 100. At the same gain, the LT1167's VOST is 63V. At gains of 10 or 100, the LT1920's maximum gain error is 0.3% and its maximum gain nonlinearity is 30ppm. At the same gains, the LT1167's maximum gain error is 0.1% and its maximum gain nonlinearity is 15ppm. Table 6 summarizes the performance of Figure 37's circuit using the LT1167.
2 DIFFERENTIAL INPUT RG** 1 8 3
Figure 37. The LT1920 is a Simple Solution That Converts a Differential Input to a Ground Referred Single-Ended Signal for the LTC2420
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5V 0.1F VREFIN VS+ 0.1F VIN+ RG RG VIN- 7 6 0.1F 4 VS - SINGLE POINT "STAR" GROUND *OPTIONAL--SEE TEXT **RG = 49.4k/(AV - 1): USE 5.49k FOR AV = 10; 499 FOR AV = 100 USE SHORT LEAD LENGTHS R1* 47 R2* 10k C1* 1F 2 3 1 VCC VREF LTC2420 GND 4 FO 8 CS SDO SCK 5 6 7 CHIP SELECT SERIAL DATA OUT SERIAL CLOCK
LT1920
VIN
2420 F37
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LTC2420
TYPICAL APPLICATIO S
Table 5. Typical Performance of the LTC2420 ADC When Used with the LT1920 Instrumentation Amplifiers in Figure 34's Differential Digitizing Circuit
VS = 5V PARAMETER Differential Input Voltage Range Zero Error Maximum Input Current Nonlinearity Noise (Without Averaging) Noise (Averaged 64 Readings) Resolution (with Averaged Readings) Overall Accuracy (Uncalibrated) Common Mode Rejection Ratio Common Mode Range 2/-1.5** 2.2/-1.7** 8.2 1.8* 0.2* 21 17.2 7.4 0.25* 0.03* 20.6 17.3 120 11.5/-11** 11.7/-11.2** AV = 10 - 30 to 400 -160 AV = 100 - 3 to 40 - 2650 2.0 6.5 1.5* 0.19* 21.3 17.5 6.1 0.27* 0.03* 20.5 18.2 AV = 10 - 30 to 500 - 213 VS = 15V AV = 100 - 3 to 50 - 2625 TOTAL (UNITS) mV V nA ppm VRMS VRMS Bits Bits dB V
*Input referred noise for the respective gain. **Typical values based on single lab tested sample of each amplifier.
Table 6. Typical Performance of the LTC2420 ADC When Used with the LT1167 Instrumentation Amplifiers in Figure 34's Differential Digitizing Circuit
VS = 5V PARAMETER Differential Input Voltage Range Zero Error Maximum Input Current Nonlinearity Noise (Without Averaging) Noise (Averaged 64 Readings) Resolution (with Averaged Readings) Overall Accuracy (Uncalibrated) Common Mode Rejection Ratio Common Mode Range 2/-1.5** 2.2/-1.7** 4.1 1.4* 0.18* 21.4 18.2 4.4 0.19* 0.02* 21.0 18.1 120 11.5/-11** 11.7/-11.2** AV = 10 - 30 to 400 -94 AV = 100 - 3 to 40 - 1590 0.5 4.1 1.5* 0.19* 21.3 18.2 3.7 0.18* 0.02* 21.1 19.4 AV = 10 - 30 to 500 - 110 VS = 15V AV = 100 - 3 to 50 - 1470 TOTAL (UNITS) mV V nA ppm VRMS VRMS Bits Bits dB V
*Input referred noise for the respective gain. **Typical values based on single lab tested sample of each amplifier.
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LTC2420
TYPICAL APPLICATIO S
Using a Low Power Precision Reference The circuit in Figure 38 shows the connections and bypassing for an LT1461-2.5 as a 2.5V reference. The LT1461 is a bandgap reference capable of 3ppm/C temperature stability yet consumes only 45A of current. The 1k resistor between the reference and the ADC reduces the transient load changes associated with sampling and produces optimal results. This reference will not impact the noise level of the LTC2420 if signals are less than 60% full scale, and only marginally increases noise approaching full scale. Even lower power references can be used if only the lower end of the LTC2420 input range is required. A Differential to Single-Ended Analog Front End Figure 39 shows the LT1167 as a means of sensing differential signals. The noise performance of the LT1167 is such that for gains less than 200, the noise floor of the LTC2420 remains the dominant noise source. At the point where the noise of the amplifier begins to dominate, the input referred noise is essentially that of the instrumentation amplifier. The linearity of the instrumentation amplifier does, however, degrade at higher gains. As a result, if the full linearity of the LTC2420 is desired, gain in the instrumentation amplifier should be limited to less than 100, possibly requiring averaging multiple samples to extend the resolution below the noise floor. The noise level of the LT1167 at gains greater than 100 is on the order of 50nVRMS, although, 1/f noise and temperature effects may degrade this below 0.1Hz. The introduction of a filter between the amplifier and the LTC2420 may improve noise levels under some circumstances by reducing noise bandwidth. Note that temperature offset drift effects envelope detection in the input of the LT1167 if exposed to RFI, thermocouple voltages in connectors, resistors and soldered junctions can all compromise results, appearing as drift or noise. Turbulent airflow over this circuitry should be avoided.
1k 5V IN OUT 0.1F LT1461-2.5 CER GND
2420 F38
5V 5V 3.5k x4 10F 2 1 8 3 OPTIONAL 6 5 22 1F
Figure 39. A Differential to Single-Ended Analog Front End
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+
10F 16V TANT
TO LTC2420 REF
Figure 38. Low Power Reference
+
1 2 5k 3 4 LTC2420
+
LT1167
RG
-
-5V AV = 49.4k + 1 RG RECOMMENDED RG: 500, 0.1% 5ppm/C
2428 F39
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LTC2420
TYPICAL APPLICATIO S
2.048MHz Oscillator for 100sps Output Ratio The oscillator circuit shown in Figure 40 can be used to drive the FO pin, boosting the conversion rate of the LTC2420 for applications that do not require a notch at 50Hz or 60Hz. This oscillator is not sensitive to hysteresis voltage of a Schmitt trigger device as are simpler relaxation oscillators using the 74HC14 or similar devices. The circuit can be tuned over a 3:1 range with only one resistor and can be gated. The use of transmission gates could be used to shift the frequency in order to provide setable conversion rates.
100smps, FO = 2.048MHz 30smps, FO = 614.4kHz U1: 74HC14 OR EQUIVALENT
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10k 2N3904
1k 47k U1-F 12 13 HALT
5k 270pF
47k 5pF U1-A 1 10pF 2 3 U1-B 4 5 U1-E 11 10 U1-C 6
U1-D 9
2420 F40
8 TO LTC2420 FO PIN
Figure 40. 2.048MHz Oscillator for 100sps Output Rate
LTC2420
PACKAGE I FOR ATIO U W U
Dimensions in inches (millimeters) unless otherwise noted.
S8 Package 8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.189 - 0.197* (4.801 - 5.004) 8 7 6 5
0.228 - 0.244 (5.791 - 6.197)
0.150 - 0.157** (3.810 - 3.988)
1 0.010 - 0.020 x 45 (0.254 - 0.508) 0.008 - 0.010 (0.203 - 0.254) 0- 8 TYP
2
3
4
0.053 - 0.069 (1.346 - 1.752)
0.004 - 0.010 (0.101 - 0.254)
0.014 - 0.019 (0.355 - 0.483) TYP *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
0.016 - 0.050 (0.406 - 1.270)
0.050 (1.270) BSC
SO8 1298
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
35
LTC2420
TYPICAL APPLICATIO
The circuit shown in Figure 41 enables pseudodifferential measurements of several bridge transducers and absolute temperature measurement. The LTC1391 is an 8-to-1 analog multiplexer. Consecutive readings are performed on each side of the bridge by selecting the appropriate channel on the LTC1391. Each output is digitized and the results digitally subtracted to obtain the pseudodifferential result. Several bridge transducers may be digitized in this manner.
THERMOCOUPLE CH0 VCC CH1 LTC1391 CH2 CH3 OUT CH4 CH5 CH6 CH7 VREF VCC FO LTC2420 VIN GND GND SCK SDO CS
2420 F41
THERMISTOR
Figure 41. Pseudodifferential Multichannel Bridge Digitizer and Digital Cold Junction Compensation
RELATED PARTS
PART NUMBER LT1019 LT1025 LTC1043 LTC1050 LT1236A-5 LTC1391 LT1460 LTC2400 LTC2401/LTC2402 LTC2404/LTC2408 LTC2410 LTC2411 LTC2413 LTC2424/LTC2428 DESCRIPTION Precision Bandgap Voltage Reference, 2.5V, 5V Micropower Thermocouple Cold Junction Compensator Dual Precision Instrumentation Switched Capacitor Building Block Precision Chopper Stabilized Op Amp Precision Bandgap Voltage Reference, 5V 8-Channel Multiplexer Micropower Series Voltage Reference 24-Bit Power, No Latency ADC in SO-8 1-/2-Channel, 24-Bit No Latency ADCs 4-/8-Channel, 24-Bit No Latency ADC 24-Bit No Latency ADC with Differential Inputs 24-Bit No Latency ADC with Differential Inputs/Reference 24-Bit No Latency ADC 4-/8-Channel 20-Bit No Latency ADCs COMMENTS 3ppm/C Drift, 0.05% Max 0.5C Initial Accuracy, 80A Supply Current Precise Charge, Balanced Switching, Low Power No External Components 5V Offset, 1.6VP-P Noise 0.05% Max, 5ppm/C Drift Low RON: 45, Low Charge Injection, Serial Interface 0.075% Max, 10ppm/C Max Drift, 2.5V, 5V and 10V Versions 4ppm INL, 10ppm TUE, 200A, Pin Compatible with LTC2420 24 Bits in MSOP Package 4ppm INL, 10ppm TUE, 200A 800nV Noise, Differential Reference, 2.7V to 5.5V Operation 1.6V Noise, Fully Differential, 10-Lead MSOP Package Simultaneous 50Hz to 60Hz Rejection 0.16ppm Noise 8ppm INL, 1.2ppm Noise, Fast Mode
36
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com
U
In order to measure absolute temperature with a thermocouple, cold junction compensation must be performed. Channel 6 measures the output of the thermocouple while channel 7 measures the output of the cold junction sensor (diode, thermistor, etc.). This enables digital cold junction compensation of the thermocouple output. The temperature measurement may then be used to compensate the temperature effects of the bridge transducers.
2420f LT/LCG 1000 4K * PRINTED IN USA (c) LINEAR TECHNOLOGY CORPORATION 2000

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